Added `clearBackupSRAM` function

miosix/arch/common/drivers/stm32_backup_domain.cpp

@@ -45,6 +45,12 @@
 #define PWR_CR1 PWR->CR1
 #endif
 
+extern unsigned char _preserve_start asm("_preserve_start");
+extern unsigned char _preserve_end asm("_preserve_end");
+
+static unsigned char *preserve_start = &_preserve_start;
+static unsigned char *preserve_end   = &_preserve_end;
+
 namespace miosix
 {
 
@@ -90,9 +96,14 @@ void BackupDomain::disableBackupSRAM()
     PWR_CSR1 &= ~PWR_CSR1_BRE;
 }
 
+void clearBackupSRAM()
+{
+    memset(preserve_start, 0, preserve_end - preserve_start);
+}
+
 BackupDomain::BackupDomain()
 {
-    // Retrive last reset reason and clear the pending flag
+    // Retrieve last reset reason and clear the pending flag
     readResetRegister();
 }
 

miosix/arch/common/drivers/stm32_backup_domain.h

@@ -40,7 +40,7 @@ enum class ResetReason
     RST_LOW_PWR         = 0,  // Low power
     RST_WINDOW_WDG      = 1,  // Reset from the windows watchdog
     RST_INDEPENDENT_WDG = 2,  // Reset from the independent watchdog
-    RST_SW              = 3,  // Sofware reset
+    RST_SW              = 3,  // Software reset
     RST_POWER_ON        = 4,  // System power on
     RST_PIN             = 5,  // Reset pin
     RST_UNKNOWN         = 6,  // Unknown
@@ -79,6 +79,11 @@ public:
      */
     void disableBackupSRAM();
 
+    /**
+     * Clear the backup SRAM.
+     */
+    void clearBackupSRAM();
+
     /**
      * Return the cause of the last reset of the micro controller
      */

miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/bsp.cpp

@@ -45,7 +45,6 @@
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
 #include "drivers/sd_stm32f2_f4_f7.h"
-#include "drivers/stm32_sgm.h"
 #include "board_settings.h"
 
 namespace miosix {
@@ -188,10 +187,6 @@ void configureSdram()
 
 void IRQbspInit()
 {
-
-    /* force Safe Guard Memory constructor call */
-    SGM::instance();
-    
     /*If using SDRAM GPIOs are enabled by configureSdram(), else enable them here */
     #ifndef __ENABLE_XRAM
     RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |