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Commit c31e8f2e authored by Alberto Nidasio's avatar Alberto Nidasio
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[Pyxis] Fixed wrong serial port configuration

parent 0e18a715
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...@@ -64,7 +64,7 @@ const unsigned int AUX_TIMER_CLOCK = 100000; ...@@ -64,7 +64,7 @@ const unsigned int AUX_TIMER_CLOCK = 100000;
const unsigned int AUX_TIMER_MAX = 0xffff; ///<\internal Aux timer is 16 bits const unsigned int AUX_TIMER_MAX = 0xffff; ///<\internal Aux timer is 16 bits
/// Serial port /// Serial port
const unsigned int defaultSerial = 4; const unsigned int defaultSerial = 1;
const unsigned int defaultSerialSpeed = 115200; const unsigned int defaultSerialSpeed = 115200;
const bool defaultSerialFlowctrl = false; const bool defaultSerialFlowctrl = false;
// #define SERIAL_1_DMA // #define SERIAL_1_DMA
......
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