Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
Skyward Boardcore
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Package registry
Container registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
Emilio Corigliano
Skyward Boardcore
Commits
db156365
Commit
db156365
authored
2 years ago
by
Alberto Nidasio
Browse files
Options
Downloads
Patches
Plain Diff
[SPI] Better commented frame format configuration for stm32f7 microcontrollers
parent
493028f9
No related branches found
No related tags found
No related merge requests found
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
src/shared/drivers/spi/SPIBus.h
+19
-1
19 additions, 1 deletion
src/shared/drivers/spi/SPIBus.h
with
19 additions
and
1 deletion
src/shared/drivers/spi/SPIBus.h
+
19
−
1
View file @
db156365
...
...
@@ -88,8 +88,16 @@ public:
void
disable
();
#ifdef _ARCH_CORTEXM7_STM32F7
/**
* @brief Set the RFFIFO threshold to generate the RXNE event when the FIFO
* level is greater than or equal to 8 bit.
*/
void
set8bitRXNE
();
/**
* @brief Set the RFFIFO threshold to generate the RXNE event when the FIFO
* level is greater than or equal to 16 bit.
*/
void
set16bitRXNE
();
#endif
...
...
@@ -309,6 +317,15 @@ inline void SPIBus::enable() { spi->CR1 |= SPI_CR1_SPE; }
inline
void
SPIBus
::
disable
()
{
spi
->
CR1
&=
~
SPI_CR1_SPE
;
}
/**
* The SPI peripheral differs on stm32f7 microcontrollers. Refer to AN4660 for a
* comprehensive differences list between different peripherals versions.
*
* The main difference here is that on the f7 you can transmit between 4 and 16.
* There is also a 32bit fifo and a threshold that generates the RXNE event.
* For this reason, on f7s we need to configure the 16 bit frame format
* differently and change the fifo threshold level.
*/
#ifndef _ARCH_CORTEXM7_STM32F7
inline
void
SPIBus
::
set8BitFrameFormat
()
{
spi
->
CR1
&=
~
SPI_CR1_DFF
;
}
...
...
@@ -426,7 +443,8 @@ inline void SPIBus::configure(SPIBusConfig newConfig)
setMasterConfiguration
();
#ifdef _ARCH_CORTEXM7_STM32F7
// By default we use 8 bit transactions
// By default the driver uses 8 bit transactions. Therefore, for f7s,
// configure the FIFO threshold to 8 bit
set8bitRXNE
();
#endif
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment