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Commit e99ff0ad authored by Alain Carlucci's avatar Alain Carlucci
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[DMA] Added FEIF5 comment

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......@@ -57,6 +57,9 @@ void __attribute__((used)) SPI1rxDmaHandlerImpl()
error = true;
fifoFaultCtr++;
}
// FEIF5 is not checked because is ALWAYS 1 both if FIFO is enabled
// or disabled. Tests show that all data are transferred correctly!
if(DMA2->HISR & (DMA_HISR_TEIF5 | DMA_HISR_DMEIF5))
{
error = true;
......
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