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  11. Feb 10, 2023
    • Emilio Corigliano's avatar
      [I2C] Enhanced I2C driver by moving logic into the ISR · 0c2b2559
      Emilio Corigliano authored
      - The driver logic has been moved directly into the Interrupt Service Routine for events so that the delay for a read or a write is drastically reduced. Now the thread, after setting up peripheral, start condition generation and address sending, is waken up only if the operation completed or an error occurred. Avoiding to wake up at every event the thread executing I2C operations reduces context switches and delay in the completion of the operation.
      - Now errors are better handled. A user can request the last error(s) occurred.
      - The support for 10-bit addressing is removed to simplify the driver and to avoid having something not tested in the main branch.
      0c2b2559
  12. Jan 20, 2023
    • Emilio Corigliano's avatar
      [I2C] Created new low-level (for stm32f4) and high-level I2C drivers · 187441af
      Emilio Corigliano authored
      Low-level driver features (specific for the stm32f4 family):
      - 7-bit (tested) and 10-bit (not tested yet) addressing;
      - Speed modes: Standard (100kHz clock) and Fast (400kHz clock);
      - Compatibility with all I2C peripherals till I2C4 (easy to extend to additional ones);
      - Internal configuration of the pins in order to avoid forgetting to set them to ALTERNATE_OD mode (so, avoiding possibility of short-circuits between master and slave);
      - The configurations of the slave (slave address, addressing mode and speed mode) we want to communicate with are setted before each read/write on the bus;
      - Support for the reStart condition when wanting to write and then read from the same slave;
      - Usage of interrupts when possible; In two cases we need polling anyway (limited to a parameter to avoid infinite polling): 
          . I2C_SR2_BUSY doesn't generate an interrupt and we can't communicate with the bus in BUSY state. 
          . I2C_SR1_SB do generate an interrupt, but its handling is a bit tricky since other interrupts are generated in the case of a reStart condition; also, using the interrupt for this, there would be the risk of a deadlock.
      - Resilience to bus deadlocks;
      
      High-level driver features:
      - Resilience to bus deadlocks embedded before any operation on the bus;
      - Implementation of higher level methods for using the bus;
      - Possibility to have a synchronized version of the driver;
      187441af
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