- Mar 17, 2023
-
-
-
Alberto Nidasio authored
-
-
-
- Mar 15, 2023
-
-
Alberto Nidasio authored
-
Alberto Nidasio authored
-
Alberto Nidasio authored
-
Alberto Nidasio authored
-
Alberto Nidasio authored
Also moved the writeBit config from SPITransaction to SPIConfig and added a byteOrder option used in registers reads and write.
-
Alberto Nidasio authored
-
Alberto Nidasio authored
-
Alberto Nidasio authored
-
- Mar 10, 2023
-
-
Matteo Pignataro authored
-
- Mar 08, 2023
-
-
Matteo Pignataro authored
-
Matteo Pignataro authored
-
- Feb 26, 2023
-
-
Matteo Pignataro authored
-
Davide Mor authored
-
- Feb 25, 2023
-
-
Matteo Pignataro authored
-
- Feb 24, 2023
-
-
Matteo Pignataro authored
-
- Feb 21, 2023
-
-
Matteo Pignataro authored
-
- Feb 20, 2023
-
-
Matteo Pignataro authored
-
- Feb 16, 2023
-
-
Matteo Pignataro authored
-
Matteo Pignataro authored
-
- Feb 10, 2023
-
-
Emilio Corigliano authored
- The driver logic has been moved directly into the Interrupt Service Routine for events so that the delay for a read or a write is drastically reduced. Now the thread, after setting up peripheral, start condition generation and address sending, is waken up only if the operation completed or an error occurred. Avoiding to wake up at every event the thread executing I2C operations reduces context switches and delay in the completion of the operation. - Now errors are better handled. A user can request the last error(s) occurred. - The support for 10-bit addressing is removed to simplify the driver and to avoid having something not tested in the main branch.
-
- Jan 20, 2023
-
-
Emilio Corigliano authored
Low-level driver features (specific for the stm32f4 family): - 7-bit (tested) and 10-bit (not tested yet) addressing; - Speed modes: Standard (100kHz clock) and Fast (400kHz clock); - Compatibility with all I2C peripherals till I2C4 (easy to extend to additional ones); - Internal configuration of the pins in order to avoid forgetting to set them to ALTERNATE_OD mode (so, avoiding possibility of short-circuits between master and slave); - The configurations of the slave (slave address, addressing mode and speed mode) we want to communicate with are setted before each read/write on the bus; - Support for the reStart condition when wanting to write and then read from the same slave; - Usage of interrupts when possible; In two cases we need polling anyway (limited to a parameter to avoid infinite polling): . I2C_SR2_BUSY doesn't generate an interrupt and we can't communicate with the bus in BUSY state. . I2C_SR1_SB do generate an interrupt, but its handling is a bit tricky since other interrupts are generated in the case of a reStart condition; also, using the interrupt for this, there would be the risk of a deadlock. - Resilience to bus deadlocks; High-level driver features: - Resilience to bus deadlocks embedded before any operation on the bus; - Implementation of higher level methods for using the bus; - Possibility to have a synchronized version of the driver;
-
- Dec 22, 2022
-
-
- Dec 08, 2022
-
-
Emilio Corigliano authored
- Created two methods getAPBTimersClock() and getAPBPeripheralsClock() - Fixed wrong computation of APB2 frequency - Previous usages of getAPBFrequency() now use getAPBTimersClock() for usage compatibility
-
- Dec 06, 2022
-
-
- Dec 04, 2022
-
-
- Nov 30, 2022
-
-
- Nov 29, 2022
-
-
- Nov 27, 2022
-
-
Matteo Pignataro authored
-
Matteo Pignataro authored
-
Matteo Pignataro authored
-
Alberto Nidasio authored
-
- Oct 24, 2022
-
-
Alberto Nidasio authored
-
Alberto Nidasio authored
-
- Oct 11, 2022
-
- Oct 08, 2022
-
-
Alberto Nidasio authored
-
Davide Mor authored
-