.gitignore

@@ -2,6 +2,7 @@
 miosix/_doc/doxygen/html/*
 
 # Exclude temporary files
+build/
 main.elf
 main.bin
 main.hex

.gitlab-ci.yml

+# Copyright (c) 2022 Skyward Experimental Rocketry
+# Author: Damiano Amatruda
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+variables:
+  GIT_SUBMODULE_STRATEGY: recursive
+
+stages:
+  - build
+
+# Stage build
+
+build:
+  stage: build
+  tags:
+    - miosix
+  script:
+    - ./miosix/_tools/testsuite/build.sh

CMakeLists.txt

+# Copyright (c) 2021 Skyward Experimental Rocketry
+# Author: Damiano Amatruda
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+cmake_minimum_required(VERSION 3.16)
+project(MiosixProject C CXX ASM)
+
+set(OPT_BOARD "" CACHE STRING "Target board")
+if(NOT OPT_BOARD)
+    message(FATAL_ERROR "No board selected")
+endif()
+
+add_subdirectory(miosix EXCLUDE_FROM_ALL)
+
+add_executable(main main.cpp)
+target_link_libraries(main PRIVATE Miosix::Miosix::${OPT_BOARD})
+add_custom_command(
+    TARGET main POST_BUILD
+    COMMAND ${CMAKE_OBJCOPY} -O ihex main main.hex
+    COMMAND ${CMAKE_OBJCOPY} -O binary main main.bin
+    BYPRODUCTS main.hex main.bin
+)

Makefile

 ##
 ## Makefile for Miosix embedded OS
 ##
-MAKEFILE_VERSION := 1.09
+MAKEFILE_VERSION := 1.09S
 GCCMAJOR := $(shell arm-miosix-eabi-gcc --version | \
                     perl -e '$$_=<>;/\(GCC\) (\d+)/;print "$$1"')
+
 ## Path to kernel directory (edited by init_project_out_of_git_repo.pl)
 KPATH := miosix
 ## Path to config directory (edited by init_project_out_of_git_repo.pl)

Readme.md

+# Miosix for Skyward
+
+This is a fork of the original fedetft/miosix-kernel repo made for Skyward Experimental Rocketry. Every Skyward-related stuff, like new boards or experimental features should be pushed here.
+
+**IMPORTANT:** when you modify this repo, remember to update the submodule in the repo that includes it.
+
+You can find information on how to configure and use the kernel
+at the following url: http://miosix.org
+
+
+### Main Differences
+
+A part from additional boards, there are some important differences with the original kernel version:
+
+1. `miosix/config/Makefile.inc`: The version of the makefile must be `1.09S`, to distinguish this kernel from the official one
+
+```
+ifneq ($(MAKEFILE_VERSION),1.09S)
+    $(info You are using an incompatible makefile. Make sure it matches \
+      the one distributed with the current version of the kernel)
+    $(error Error)
+endif
+```
+
+2. `miosix/config/miosix`: The usual `error` is commented out and `JTAG` enabled by default
+
+3. `CMakeLists.txt`, `miosix/CMakeLists.txt`, `miosix/config/options.cmake` and `miosix/config/boards.cmake`: CMake is supported
+
+Note that these changes must be respected when pulling from the original repo
+
+
+### Pulling from Original Repo
+
+If you wish to pull from the original kernel repo you should:
+
+```
+git pull https://github.com/fedetft/miosix-kernel.git testing
+```
+
+Then merge (keeping the 1.09S check in the Makefiles), commit and push.
+
+Note that the testing branch is were normally the latest updates
+are made for the Skyward guys.

Readme.txt

-
-Welcome to the Miosix kernel
-============================
-
-You can find information on how to configure and use the kernel
-at the following url: http://miosix.org
-

miosix/CMakeLists.txt

+# Copyright (c) 2021-2022 Skyward Experimental Rocketry
+# Authors: Damiano Amatruda, Michele Scuttari
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+cmake_minimum_required(VERSION 3.16)
+project(Miosix C CXX ASM)
+
+set(KPATH ${CMAKE_CURRENT_LIST_DIR})
+
+include(${KPATH}/config/boards.cmake)
+
+foreach(OPT_BOARD ${BOARDS})
+    set(DFLAGS -MMD -MP)
+    include(${KPATH}/config/options.cmake)
+
+    function(set_miosix_properties TARGET)
+        target_include_directories(${TARGET} PUBLIC
+            ${KPATH}/config
+            ${KPATH}/config/${BOARD_INC}
+            ${KPATH}
+            ${KPATH}/arch/common
+            ${KPATH}/${ARCH_INC}
+            ${KPATH}/${BOARD_INC}
+        )
+        target_compile_definitions(${TARGET} PUBLIC $<$<CONFIG:Debug>:DEBUG> PRIVATE COMPILING_MIOSIX)
+        target_compile_features(${TARGET} PUBLIC cxx_std_14)
+        target_compile_options(${TARGET} PUBLIC
+            ${DFLAGS}
+            $<$<COMPILE_LANGUAGE:C>:${CFLAGS_BASE}>
+            $<$<COMPILE_LANGUAGE:CXX>:${CXXFLAGS_BASE}>
+            $<$<COMPILE_LANGUAGE:ASM>:${AFLAGS_BASE}>
+        )
+        set_property(TARGET ${TARGET} PROPERTY INTERFACE_LINK_DEPENDS ${LINKER_SCRIPT})
+        target_link_options(${TARGET} INTERFACE ${LFLAGS_BASE})
+        target_link_libraries(${TARGET} INTERFACE stdc++ c m gcc atomic)
+    endfunction()
+
+    set(STAGE_1_BOOT stage_1_boot-${OPT_BOARD})
+    add_library(${STAGE_1_BOOT} OBJECT ${BOOT_FILE})
+    set_miosix_properties(${STAGE_1_BOOT})
+
+    set(MIOSIX_LIBRARY miosix-${OPT_BOARD})
+    add_library(${MIOSIX_LIBRARY} STATIC
+        kernel/kernel.cpp
+        kernel/sync.cpp
+        kernel/error.cpp
+        kernel/pthread.cpp
+        kernel/stage_2_boot.cpp
+        kernel/elf_program.cpp
+        kernel/process.cpp
+        kernel/process_pool.cpp
+        kernel/timeconversion.cpp
+        kernel/SystemMap.cpp
+        kernel/scheduler/priority/priority_scheduler.cpp
+        kernel/scheduler/control/control_scheduler.cpp
+        kernel/scheduler/edf/edf_scheduler.cpp
+        filesystem/file_access.cpp
+        filesystem/file.cpp
+        filesystem/stringpart.cpp
+        filesystem/console/console_device.cpp
+        filesystem/mountpointfs/mountpointfs.cpp
+        filesystem/devfs/devfs.cpp
+        filesystem/fat32/fat32.cpp
+        filesystem/fat32/ff.cpp
+        filesystem/fat32/diskio.cpp
+        filesystem/fat32/wtoupper.cpp
+        filesystem/fat32/ccsbcs.cpp
+        stdlib_integration/libc_integration.cpp
+        stdlib_integration/libstdcpp_integration.cpp
+        e20/e20.cpp
+        e20/unmember.cpp
+        util/util.cpp
+        util/unicode.cpp
+        util/version.cpp
+        util/crc16.cpp
+        util/lcd44780.cpp
+        ${ARCH_SRC}
+    )
+    add_library(Miosix::Miosix::${OPT_BOARD} ALIAS ${MIOSIX_LIBRARY})
+    target_sources(${MIOSIX_LIBRARY} INTERFACE $<TARGET_OBJECTS:${STAGE_1_BOOT}>)
+    set_miosix_properties(${MIOSIX_LIBRARY})
+    add_custom_command(
+        TARGET ${MIOSIX_LIBRARY} POST_BUILD
+        COMMAND perl ${KPATH}/_tools/kernel_global_objects.pl $<TARGET_OBJECTS:${MIOSIX_LIBRARY}>
+        VERBATIM
+        COMMAND_EXPAND_LISTS
+    )
+endforeach()
+
+add_subdirectory(_tools/testsuite EXCLUDE_FROM_ALL)

miosix/Makefile

@@ -2,9 +2,10 @@
 ## Makefile for Miosix embedded OS
 ## This makefile builds the whole kernel
 ##
-MAKEFILE_VERSION := 1.09
+MAKEFILE_VERSION := 1.09S
 GCCMAJOR := $(shell arm-miosix-eabi-gcc --version | \
                     perl -e '$$_=<>;/\(GCC\) (\d+)/;print "$$1"')
+
 ## KPATH and CONFPATH are forwarded by the parent Makefile
 include $(CONFPATH)/config/Makefile.inc
 

miosix/_doc/textdoc/stm32-bootloader.txt

@@ -76,7 +76,7 @@ interrupts @ 0x6800000, or Miosix will fail at the first interrupt.
 
 Then run openocd in a shell:
 
-sudo openocd -f miosix/arch/cortexM3_stm32/stm32f103ze_stm3210e-eval/stm32f10x_eval.cfg
+sudo openocd -f miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32f10x_eval.cfg
 
 and in another shell type:
 

miosix/_tools/testsuite/CMakeLists.txt

+# Copyright (c) 2022 Skyward Experimental Rocketry
+# Authors: Damiano Amatruda
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+add_custom_target(miosix-testsuite)
+
+# Use only the board where the testsuite has a chance to compile
+set(BOARDS
+    stm32f103ze_stm3210e-eval
+    stm32f103ve_mp3v2
+    stm32f103ve_strive_mini
+    stm32f103ze_redbull_v2
+    stm32f407vg_stm32f4discovery
+    stm32f207zg_ethboard_v2
+    stm32f205rg_sony-newman
+    stm32f407vg_bitsboard
+    stm32f429zi_stm32f4discovery
+    stm32f429zi_oledboard2
+    efm32gg332f1024_wandstem
+    stm32f411re_nucleo
+    stm32f429zi_skyward_anakin
+    stm32f100rc_solertegiard
+    stm32f205rc_skyward_stormtrooper
+    stm32f205rc_skyward_ciuti
+    stm32f401vc_stm32f4discovery
+    stm32f469ni_stm32f469i-disco
+    stm32f429zi_skyward_homeone
+    stm32f429zi_skyward_rogallina
+    stm32f401re_nucleo
+    stm32f746zg_nucleo
+    stm32h753xi_eval
+    stm32f407vg_thermal_test_chip
+    stm32f205_generic
+    stm32f429zi_skyward_death_stack
+    stm32f429zi_skyward_death_stack_x
+    stm32f429zi_skyward_death_stack_x_maker_faire
+    stm32f407vg_skyward_tortellino
+    stm32f411ce_blackpill
+    stm32f429zi_hre_test_stand
+)
+
+foreach(OPT_BOARD ${BOARDS})
+    set(KERNEL_TESTSUITE miosix-testsuite-${OPT_BOARD})
+    add_executable(${KERNEL_TESTSUITE} ${KPATH}/_tools/testsuite/testsuite.cpp)
+    target_link_libraries(${KERNEL_TESTSUITE} PRIVATE Miosix::Miosix::${OPT_BOARD})
+    add_custom_command(
+        TARGET ${KERNEL_TESTSUITE} POST_BUILD
+        COMMAND ${CMAKE_OBJCOPY} -O ihex ${KERNEL_TESTSUITE} ${KERNEL_TESTSUITE}.hex
+        COMMAND ${CMAKE_OBJCOPY} -O binary ${KERNEL_TESTSUITE} ${KERNEL_TESTSUITE}.bin
+        BYPRODUCTS ${KERNEL_TESTSUITE}.hex ${KERNEL_TESTSUITE}.bin
+    )
+    add_dependencies(miosix-testsuite ${KERNEL_TESTSUITE})
+endforeach()

miosix/_tools/testsuite/build.sh

+#!/bin/bash
+
+# Copyright (c) 2022 Skyward Experimental Rocketry
+# Authors: Damiano Amatruda
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+set -e
+
+cd -- "$(dirname "$0")/../.."
+
+cmake \
+    -Bbuild \
+    -DCMAKE_TOOLCHAIN_FILE=_tools/toolchain.cmake \
+    -DCMAKE_C_COMPILER_LAUNCHER=ccache -DCMAKE_CXX_COMPILER_LAUNCHER=ccache \
+    -DCMAKE_BUILD_TYPE=Release \
+    -GNinja \
+    .
+
+cmake --build build --target miosix-testsuite

miosix/_tools/toolchain.cmake

+# Copyright (c) 2021 Skyward Experimental Rocketry
+# Author: Damiano Amatruda
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+set(CMAKE_SYSTEM_NAME Linux)
+set(CMAKE_SYSTEM_PROCESSOR arm)
+
+# Select compiler
+set(PREFIX arm-miosix-eabi-)
+
+# From compiler prefix form the name of the compiler and other tools
+set(CMAKE_C_COMPILER ${PREFIX}gcc)
+set(CMAKE_CXX_COMPILER ${PREFIX}g++)
+set(CMAKE_AR ${PREFIX}ar)
+set(CMAKE_ASM_COMPILER ${PREFIX}as)
+set(CMAKE_OBJCOPY ${PREFIX}objcopy)
+set(CMAKE_OBJDUMP ${PREFIX}objdump)
+set(CMAKE_SIZE ${PREFIX}size)
+
+set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
+set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)

miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c

@@ -356,8 +356,10 @@ static void SetSysClock(void)
 /******************************************************************************/
 /*            PLL (clocked by HSE) used as System clock source                */
 /******************************************************************************/
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
   
+#ifndef USE_INTERNAL_CLOCK
+
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
   /* Enable HSE */
   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
  
@@ -418,10 +420,76 @@ static void SetSysClock(void)
     }
   }
   else
-  { /* If HSE fails to start-up, the application will have wrong clock
+  {
+#endif
+     /* If HSE fails to start-up, the application will have wrong clock
          configuration. User can add here some code to deal with this error */
+         
+    /*Thanks, I will add some code, by LE, MF, PM in the role of cursing colleagues*/
+
+     /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    RCC_SYNC();
+    PWR->CR |= PWR_CR_VOS;
+
+    /* HCLK = SYSCLK / 1*/
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK / 2*/
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+    
+    /* PCLK1 = HCLK / 4*/
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    RCC->CR &= ~((uint32_t)RCC_CR_HSEON);
+
+    RCC->CR |= ((uint32_t)RCC_CR_HSION);
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= ~((uint32_t)RCC_CR_HSEBYP);
+
+    /* Set HSI as input to PLL */
+    RCC->PLLCFGR &= ~((uint32_t)RCC_PLLCFGR_PLLSRC);
+
+    /* Reset PLLM bits */
+    RCC->PLLCFGR &= ~((uint32_t)0x3F);
+
+    /* Set PLLM bits to have VCO input frequency to 1 MHz */
+    RCC->PLLCFGR |= (uint32_t)16;
+
+    /* Reset PLLN bits to 0 */
+    RCC->PLLCFGR &= 0xFFFF803F;
+    /* Set PLLN - HSI multiplier to reach 336 MHz */
+    RCC->PLLCFGR |= (uint32_t)336 << 6;
+
+    /* Set PLLQ to configure SDIO, USB OTG and RNG */    
+    RCC->PLLCFGR |= (uint32_t)7 << 24;
+
+    /* Set PLLP to 2 to reach 168 MHz */
+    RCC->PLLCFGR &= ~((uint32_t)(RCC_PLLCFGR_PLLP_0 | RCC_PLLCFGR_PLLP_1));
+
+    /* Enable the main PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
     }
    
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+
+    /* Select the main PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL)
+    {
+    }
+#ifndef USE_INTERNAL_CLOCK
+  }
+#endif
 }
 // By TFT -- end
 

miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h

@@ -7,7 +7,7 @@
   *          This file contains:
   *           - Data structures and the address mapping for all peripherals
   *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripherals registers hardware
+  *           - Macros to access peripheral�s registers hardware
   *
   ******************************************************************************
   * @attention
@@ -10800,6 +10800,9 @@ typedef struct
 #define RCC_APB1ENR_LPTIM1EN_Pos           (9U)                                
 #define RCC_APB1ENR_LPTIM1EN_Msk           (0x1U << RCC_APB1ENR_LPTIM1EN_Pos)  /*!< 0x00000200 */
 #define RCC_APB1ENR_LPTIM1EN               RCC_APB1ENR_LPTIM1EN_Msk            
+#define RCC_APB1ENR_RTCEN_Pos              (10U)                               
+#define RCC_APB1ENR_RTCEN_Msk              (0x1U << RCC_APB1ENR_RTCEN_Pos)     /*!< 0x00000400 */
+#define RCC_APB1ENR_RTCEN                  RCC_APB1ENR_RTCEN_Msk
 #define RCC_APB1ENR_WWDGEN_Pos             (11U)                               
 #define RCC_APB1ENR_WWDGEN_Msk             (0x1U << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
 #define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk              

miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c

@@ -98,6 +98,36 @@
                                    This value must be a multiple of 0x200. */
 /******************************************************************************/
 
+// By Alberto Nidasio and TFT -- begin
+#if (HSE_VALUE % 2000000) == 0
+
+//PLL input frequency set to 2MHz to reduce jitter as suggested by the datasheet.
+const unsigned int PLL_M=HSE_VALUE/2000000;
+#ifdef SYSCLK_FREQ_216MHz
+const unsigned int PLL_Q=9;
+const unsigned int PLL_R=7;
+const unsigned int PLL_N=216;
+const unsigned int PLL_P=2;
+#else
+#error Clock not selected
+#endif
+
+#else // HSE_VALUE not divisible by 2MHz
+
+//PLL Input frequency set to 1MHz
+const unsigned int PLL_M=HSE_VALUE/1000000;
+#ifdef SYSCLK_FREQ_216MHz
+const unsigned int PLL_Q=9;
+const unsigned int PLL_R=7;
+const unsigned int PLL_N=432;
+const unsigned int PLL_P=2;
+#else
+#error Clock not selected
+#endif
+
+#endif // HSE_VALUE divisibility check
+// By Alberto Nidasio and TFT -- end
+
 /**
   * @}
   */
@@ -292,15 +322,6 @@ void SetSysClk(void)
 /*            PLL (clocked by HSE) used as System clock source                */
 /******************************************************************************/
   
-/************************* PLL Parameters for clock at 216MHz******************/
-  //By TFT: the original settings were for a boar with a 25MHz clock, not 8MHz
-  //They also mention a PLL_R that doesn't exist in the datasheet and maps to
-  //reseved bits. Finally, the PLL input frequency was set to 2MHz to reduce
-  //PLL jitter as suggested by the datasheet.
-  
-  //uint32_t PLL_M = 25,PLL_Q = 9, PLL_R = 7, PLL_N = 432, PLL_P = 2;
-  uint32_t PLL_M = 4,PLL_Q = 9, PLL_R = 7, PLL_N = 216, PLL_P = 2;
-  
   /* Enable Power Control clock */
   RCC->APB1ENR |= RCC_APB1ENR_PWREN;
  

miosix/arch/common/core/interrupts.h

@@ -3,7 +3,7 @@
 
 #ifdef _ARCH_ARM7_LPC2000
 #include "interrupts_arm7.h"
-#elif defined(_ARCH_CORTEXM0_STM32)   || defined(_ARCH_CORTEXM3_STM32)   \
+#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM3_STM32F1) \
    || defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32F2) \
    || defined(_ARCH_CORTEXM3_STM32L1) || defined(_ARCH_CORTEXM7_STM32F7) \
    || defined(_ARCH_CORTEXM7_STM32H7) || defined(_ARCH_CORTEXM3_EFM32GG) \
@@ -13,11 +13,3 @@
 #else
 #error "Unknown arch"
 #endif
-
-// Cortex M0 and M0+ does not have some SCB registers, in order to avoid
-// compilation issues a flag is defined to disable code that accesses to 
-// registers not present in these families
-
-#if defined(_ARCH_CORTEXM0_STM32)
-#define _ARCH_CORTEXM0
-#endif

miosix/arch/common/core/interrupts_cortexMx.cpp

@@ -99,20 +99,20 @@ void __attribute__((noinline)) HardFault_impl()
     #ifdef WITH_ERRLOG
     IRQerrorLog("\r\n***Unexpected HardFault @ ");
     printUnsignedInt(getProgramCounter());
-    #ifndef _ARCH_CORTEXM0
+    #if !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM0_STM32G0) && !defined(_ARCH_CORTEXM0_STM32L0)
     unsigned int hfsr=SCB->HFSR;
     if(hfsr & 0x40000000) //SCB_HFSR_FORCED
         IRQerrorLog("Fault escalation occurred\r\n");
     if(hfsr & 0x00000002) //SCB_HFSR_VECTTBL
         IRQerrorLog("A BusFault occurred during a vector table read\r\n");
-    #endif //_ARCH_CORTEXM0
+    #endif // !_ARCH_CORTEXM0_STM32F0 && !_ARCH_CORTEXM0_STM32G0 && !_ARCH_CORTEXM0_STM32L0
     #endif //WITH_ERRLOG
     miosix_private::IRQsystemReboot();
 }
 
 // Cortex M0/M0+ architecture does not have the interrupts handled by code
 // below this point
-#ifndef _ARCH_CORTEXM0
+#if !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM0_STM32G0) && !defined(_ARCH_CORTEXM0_STM32L0)
 
 void __attribute__((naked)) MemManage_Handler()
 {
@@ -262,7 +262,7 @@ void DebugMon_Handler()
     miosix_private::IRQsystemReboot();
 }
 
-#endif //_ARCH_CORTEXM0
+#endif // !_ARCH_CORTEXM0_STM32F0 && !_ARCH_CORTEXM0_STM32G0 && !_ARCH_CORTEXM0_STM32L0
 
 void PendSV_Handler()
 {

miosix/arch/common/drivers/sd_stm32f2_f4.cpp → miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp

@@ -25,7 +25,7 @@
  *   along with this program; if not, see <http://www.gnu.org/licenses/>   *
  ***************************************************************************/
 
-#include "sd_stm32f2_f4.h"
+#include "sd_stm32f2_f4_f7.h"
 #include "interfaces/bsp.h"
 #include "interfaces/arch_registers.h"
 #include "core/cache_cortexMx.h"
@@ -52,9 +52,17 @@
  */
 #if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
 
+#if SD_SDMMC==1
 #define SDIO                 SDMMC1
 #define RCC_APB2ENR_SDIOEN   RCC_APB2ENR_SDMMC1EN
 #define SDIO_IRQn            SDMMC1_IRQn
+#elif SD_SDMMC==2
+#define SDIO                 SDMMC2
+#define RCC_APB2ENR_SDIOEN   RCC_APB2ENR_SDMMC2EN
+#define SDIO_IRQn            SDMMC2_IRQn
+#else
+#error SD_SDMMC undefined or not in range
+#endif
 
 #define SDIO_STA_STBITERR    0 //This bit has been removed
 #define SDIO_STA_RXOVERR     SDMMC_STA_RXOVERR
@@ -76,6 +84,7 @@
 #define SDIO_CLKCR_CLKEN     SDMMC_CLKCR_CLKEN
 #define SDIO_CLKCR_PWRSAV    SDMMC_CLKCR_PWRSAV
 #define SDIO_CLKCR_PWRSAV    SDMMC_CLKCR_PWRSAV
+#define SDIO_CLKCR_WIDBUS_0  SDMMC_CLKCR_WIDBUS_0
 
 #define SDIO_MASK_STBITERRIE 0 //This bit has been removed
 #define SDIO_MASK_RXOVERRIE  SDMMC_MASK_RXOVERRIE
@@ -91,16 +100,32 @@
 #define SDIO_POWER_PWRCTRL_1 SDMMC_POWER_PWRCTRL_1
 #define SDIO_POWER_PWRCTRL_0 SDMMC_POWER_PWRCTRL_0
 
+constexpr int ICR_FLAGS_CLR=0x4005ff;
+
+#else  //defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
+
+constexpr int ICR_FLAGS_CLR=0xc007ff;
+
 #endif //defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
 
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+#define DMA_Stream           DMA2_Stream0
+#else
+#define DMA_Stream           DMA2_Stream3
+#endif
+
 /**
  * \internal
- * DMA2 Stream3 interrupt handler
+ * DMA2 Stream interrupt handler
  */
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+void __attribute__((naked)) DMA2_Stream0_IRQHandler()
+#else
 void __attribute__((naked)) DMA2_Stream3_IRQHandler()
+#endif
 {
     saveContext();
-    asm volatile("bl _ZN6miosix18DMA2stream3irqImplEv");
+    asm volatile("bl _ZN6miosix12SDDMAirqImplEv");
     restoreContext();
 }
 
@@ -108,14 +133,16 @@ void __attribute__((naked)) DMA2_Stream3_IRQHandler()
  * \internal
  * SDIO interrupt handler
  */
-#if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==1
 void __attribute__((naked)) SDMMC1_IRQHandler()
+#elif (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+void __attribute__((naked)) SDMMC2_IRQHandler()
 #else //stm32f2 and stm32f4
 void __attribute__((naked)) SDIO_IRQHandler()
 #endif
 {
     saveContext();
-    asm volatile("bl _ZN6miosix11SDIOirqImplEv");
+    asm volatile("bl _ZN6miosix9SDirqImplEv");
     restoreContext();
 }
 
@@ -130,16 +157,26 @@ static unsigned int sdioFlags;      ///< \internal SDIO status flags
  * \internal
  * DMA2 Stream3 interrupt handler actual implementation
  */
-void __attribute__((used)) DMA2stream3irqImpl()
+void __attribute__((used)) SDDMAirqImpl()
 {
     dmaFlags=DMA2->LISR;
+    #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+    if(dmaFlags & (DMA_LISR_TEIF0 | DMA_LISR_DMEIF0 | DMA_LISR_FEIF0))
+        transferError=true;
+
+    DMA2->LIFCR = DMA_LIFCR_CTCIF0
+                | DMA_LIFCR_CTEIF0
+                | DMA_LIFCR_CDMEIF0
+                | DMA_LIFCR_CFEIF0;
+    #else
     if(dmaFlags & (DMA_LISR_TEIF3 | DMA_LISR_DMEIF3 | DMA_LISR_FEIF3))
         transferError=true;
 
-    DMA2->LIFCR=DMA_LIFCR_CTCIF3  |
-                DMA_LIFCR_CTEIF3  |
-                DMA_LIFCR_CDMEIF3 |
-                DMA_LIFCR_CFEIF3;
+    DMA2->LIFCR = DMA_LIFCR_CTCIF3
+                | DMA_LIFCR_CTEIF3
+                | DMA_LIFCR_CDMEIF3
+                | DMA_LIFCR_CFEIF3;
+    #endif
     
     if(!waiting) return;
     waiting->IRQwakeup();
@@ -152,14 +189,14 @@ void __attribute__((used)) DMA2stream3irqImpl()
  * \internal
  * DMA2 Stream3 interrupt handler actual implementation
  */
-void __attribute__((used)) SDIOirqImpl()
+void __attribute__((used)) SDirqImpl()
 {
     sdioFlags=SDIO->STA;
     if(sdioFlags & (SDIO_STA_STBITERR | SDIO_STA_RXOVERR  |
                     SDIO_STA_TXUNDERR | SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL))
         transferError=true;
     
-    SDIO->ICR=0x7ff;//Clear flags
+    SDIO->ICR=ICR_FLAGS_CLR; //Clear flags
     
     if(!waiting) return;
     waiting->IRQwakeup();
@@ -193,12 +230,22 @@ enum CardType
 static CardType cardType=Invalid;
 
 //SD card GPIOs
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+typedef Gpio<GPIOG_BASE,9>  sdD0;
+typedef Gpio<GPIOG_BASE,10> sdD1;
+typedef Gpio<GPIOB_BASE,3>  sdD2;
+typedef Gpio<GPIOB_BASE,4>  sdD3;
+typedef Gpio<GPIOD_BASE,6>  sdCLK;
+typedef Gpio<GPIOD_BASE,7>  sdCMD;
+#else
 typedef Gpio<GPIOC_BASE,8>  sdD0;
 typedef Gpio<GPIOC_BASE,9>  sdD1;
 typedef Gpio<GPIOC_BASE,10> sdD2;
 typedef Gpio<GPIOC_BASE,11> sdD3;
 typedef Gpio<GPIOC_BASE,12> sdCLK;
 typedef Gpio<GPIOD_BASE,2>  sdCMD;
+#endif
+
 
 //
 // Class BufferConverter
@@ -631,12 +678,12 @@ CmdResult Command::send(CommandType cmd, unsigned int arg)
         {
             if(SDIO->STA & SDIO_STA_CMDSENT)
             {
-                SDIO->ICR=0x7ff;//Clear flags
+                SDIO->ICR=ICR_FLAGS_CLR;//Clear flags
                 return CmdResult(cc,CmdResult::Ok);
             }
             delayUs(1);
         }
-        SDIO->ICR=0x7ff;//Clear flags
+        SDIO->ICR=ICR_FLAGS_CLR;//Clear flags
         return CmdResult(cc,CmdResult::Timeout);
     }
 
@@ -646,7 +693,7 @@ CmdResult Command::send(CommandType cmd, unsigned int arg)
         unsigned int status=SDIO->STA;
         if(status & SDIO_STA_CMDREND)
         {
-            SDIO->ICR=0x7ff;//Clear flags
+            SDIO->ICR=ICR_FLAGS_CLR;//Clear flags
             if(SDIO->RESPCMD==cc) return CmdResult(cc,CmdResult::Ok);
             else return CmdResult(cc,CmdResult::RespNotMatch);
         }
@@ -884,11 +931,18 @@ static void displayBlockTransferError()
 static unsigned int dmaTransferCommonSetup(const unsigned char *buffer)
 {
     //Clear both SDIO and DMA interrupt flags
-    SDIO->ICR=0x7ff;
-    DMA2->LIFCR=DMA_LIFCR_CTCIF3  |
-                DMA_LIFCR_CTEIF3  |
-                DMA_LIFCR_CDMEIF3 |
-                DMA_LIFCR_CFEIF3;
+    SDIO->ICR=ICR_FLAGS_CLR;
+    #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+    DMA2->LIFCR = DMA_LIFCR_CTCIF0
+                | DMA_LIFCR_CTEIF0
+                | DMA_LIFCR_CDMEIF0
+                | DMA_LIFCR_CFEIF0;
+    #else
+    DMA2->LIFCR = DMA_LIFCR_CTCIF3
+                | DMA_LIFCR_CTEIF3
+                | DMA_LIFCR_CDMEIF3
+                | DMA_LIFCR_CFEIF3;
+    #endif
 
     transferError=false;
     dmaFlags=sdioFlags=0;
@@ -937,24 +991,28 @@ static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk,
                SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun
                SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail
                SDIO_MASK_DTIMEOUTIE;  //Interrupt on data timeout
-	DMA2_Stream3->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
-	DMA2_Stream3->M0AR=reinterpret_cast<unsigned int>(buffer);
-	//Note: DMA2_Stream3->NDTR is don't care in peripheral flow control mode
-    DMA2_Stream3->FCR=DMA_SxFCR_FEIE    | //Interrupt on fifo error
-                      DMA_SxFCR_DMDIS   | //Fifo enabled
-                      DMA_SxFCR_FTH_0;    //Take action if fifo half full
-	DMA2_Stream3->CR=DMA_SxCR_CHSEL_2   | //Channel 4 (SDIO)
-                     DMA_SxCR_PBURST_0  | //4-beat bursts read from SDIO
-                     DMA_SxCR_PL_0      | //Medium priority DMA stream
-                     memoryTransferSize | //RAM data size depends on alignment
-					 DMA_SxCR_PSIZE_1   | //Read 32bit at a time from SDIO
-				     DMA_SxCR_MINC      | //Increment RAM pointer
-			         0                  | //Peripheral to memory direction
-                     DMA_SxCR_PFCTRL    | //Peripheral is flow controller
-			         DMA_SxCR_TCIE      | //Interrupt on transfer complete
-                     DMA_SxCR_TEIE      | //Interrupt on transfer error
-                     DMA_SxCR_DMEIE     | //Interrupt on direct mode error
-			  	     DMA_SxCR_EN;         //Start the DMA
+    DMA_Stream->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
+    DMA_Stream->M0AR=reinterpret_cast<unsigned int>(buffer);
+    //Note: DMA_Stream->NDTR is don't care in peripheral flow control mode
+    DMA_Stream->FCR = DMA_SxFCR_FEIE   //Interrupt on fifo error
+                    | DMA_SxFCR_DMDIS  //Fifo enabled
+                    | DMA_SxFCR_FTH_0; //Take action if fifo half full
+    #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+    DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) //Channel 4 (SDIO)
+    #else
+    DMA_Stream->CR = DMA_SxCR_CHSEL_2   //Channel 4 (SDIO)
+    #endif
+                   | DMA_SxCR_PBURST_0  //4-beat bursts read from SDIO
+                   | DMA_SxCR_PL_0      //Medium priority DMA stream
+                   | memoryTransferSize //RAM data size depends on alignment
+                   | DMA_SxCR_PSIZE_1   //Read 32bit at a time from SDIO
+                   | DMA_SxCR_MINC      //Increment RAM pointer
+                   | 0                  //Peripheral to memory direction
+                   | DMA_SxCR_PFCTRL    //Peripheral is flow controller
+                   | DMA_SxCR_TCIE      //Interrupt on transfer complete
+                   | DMA_SxCR_TEIE      //Interrupt on transfer error
+                   | DMA_SxCR_DMEIE     //Interrupt on direct mode error
+                   | DMA_SxCR_EN;       //Start the DMA
     
     SDIO->DLEN=nblk*512;
     if(waiting==0)
@@ -977,8 +1035,8 @@ static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk,
             }
         }
     } else transferError=true;
-    DMA2_Stream3->CR=0;
-    while(DMA2_Stream3->CR & DMA_SxCR_EN) ; //DMA may take time to stop
+    DMA_Stream->CR=0;
+    while(DMA_Stream->CR & DMA_SxCR_EN) ; //DMA may take time to stop
     SDIO->DCTRL=0; //Disable data path state machine
     SDIO->MASK=0;
 
@@ -1040,26 +1098,30 @@ static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk,
                SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun
                SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail
                SDIO_MASK_DTIMEOUTIE;  //Interrupt on data timeout
-	DMA2_Stream3->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
-	DMA2_Stream3->M0AR=reinterpret_cast<unsigned int>(buffer);
-	//Note: DMA2_Stream3->NDTR is don't care in peripheral flow control mode
+    DMA_Stream->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
+    DMA_Stream->M0AR=reinterpret_cast<unsigned int>(buffer);
+    //Note: DMA_Stream->NDTR is don't care in peripheral flow control mode
     //Quirk: not enabling DMA_SxFCR_FEIE because the SDIO seems to generate
     //a spurious fifo error. The code was tested and the transfer completes
     //successfully even in the presence of this fifo error
-    DMA2_Stream3->FCR=DMA_SxFCR_DMDIS   | //Fifo enabled
-                      DMA_SxFCR_FTH_1   | //Take action if fifo full
-                      DMA_SxFCR_FTH_0;
-	DMA2_Stream3->CR=DMA_SxCR_CHSEL_2   | //Channel 4 (SDIO)
-                     DMA_SxCR_PBURST_0  | //4-beat bursts write to SDIO
-                     DMA_SxCR_PL_0      | //Medium priority DMA stream
-                     memoryTransferSize | //RAM data size depends on alignment
-					 DMA_SxCR_PSIZE_1   | //Write 32bit at a time to SDIO
-				     DMA_SxCR_MINC      | //Increment RAM pointer
-			         DMA_SxCR_DIR_0     | //Memory to peripheral direction
-                     DMA_SxCR_PFCTRL    | //Peripheral is flow controller
-                     DMA_SxCR_TEIE      | //Interrupt on transfer error
-                     DMA_SxCR_DMEIE     | //Interrupt on direct mode error
-			  	     DMA_SxCR_EN;         //Start the DMA
+    DMA_Stream->FCR = DMA_SxFCR_DMDIS  //Fifo enabled
+                    | DMA_SxFCR_FTH_1  //Take action if fifo full
+                    | DMA_SxFCR_FTH_0;
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+    DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) // Channel 4 (SDIO)
+#else
+    DMA_Stream->CR = DMA_SxCR_CHSEL_2     // Channel 4 (SDIO)
+#endif
+                   | DMA_SxCR_PBURST_0  //4-beat bursts write to SDIO
+                   | DMA_SxCR_PL_0      //Medium priority DMA stream
+                   | memoryTransferSize //RAM data size depends on alignment
+                   | DMA_SxCR_PSIZE_1   //Write 32bit at a time to SDIO
+                   | DMA_SxCR_MINC      //Increment RAM pointer
+                   | DMA_SxCR_DIR_0     //Memory to peripheral direction
+                   | DMA_SxCR_PFCTRL    //Peripheral is flow controller
+                   | DMA_SxCR_TEIE      //Interrupt on transfer error
+                   | DMA_SxCR_DMEIE     //Interrupt on direct mode error
+                   | DMA_SxCR_EN;       //Start the DMA
     
     SDIO->DLEN=nblk*512;
     if(waiting==0)
@@ -1082,8 +1144,8 @@ static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk,
             }
         }
     } else transferError=true;
-    DMA2_Stream3->CR=0;
-    while(DMA2_Stream3->CR & DMA_SxCR_EN) ; //DMA may take time to stop
+    DMA_Stream->CR=0;
+    while(DMA_Stream->CR & DMA_SxCR_EN) ; //DMA may take time to stop
     SDIO->DCTRL=0; //Disable data path state machine
     SDIO->MASK=0;
 
@@ -1161,6 +1223,22 @@ static void initSDIOPeripheral()
         RCC_SYNC();
         RCC->APB2ENR |= RCC_APB2ENR_SDIOEN;
         RCC_SYNC();
+        #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+        sdD0::mode(Mode::ALTERNATE);
+        sdD0::alternateFunction(11);
+        #ifndef SD_ONE_BIT_DATABUS
+        sdD1::mode(Mode::ALTERNATE);
+        sdD1::alternateFunction(11);
+        sdD2::mode(Mode::ALTERNATE);
+        sdD2::alternateFunction(10);
+        sdD3::mode(Mode::ALTERNATE);
+        sdD3::alternateFunction(10);
+        #endif // SD_ONE_BIT_DATABUS
+        sdCLK::mode(Mode::ALTERNATE);
+        sdCLK::alternateFunction(11);
+        sdCMD::mode(Mode::ALTERNATE);
+        sdCMD::alternateFunction(11);
+        #else
         sdD0::mode(Mode::ALTERNATE);
         sdD0::alternateFunction(12);
         #ifndef SD_ONE_BIT_DATABUS
@@ -1175,9 +1253,16 @@ static void initSDIOPeripheral()
         sdCLK::alternateFunction(12);
         sdCMD::mode(Mode::ALTERNATE);
         sdCMD::alternateFunction(12);
+        #endif
     }
+
+    #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+    NVIC_SetPriority(DMA2_Stream0_IRQn,15);//Low priority for DMA
+    NVIC_EnableIRQ(DMA2_Stream0_IRQn);
+    #else
     NVIC_SetPriority(DMA2_Stream3_IRQn,15);//Low priority for DMA
     NVIC_EnableIRQ(DMA2_Stream3_IRQn);
+    #endif
     NVIC_SetPriority(SDIO_IRQn,15);//Low priority for SDIO
     NVIC_EnableIRQ(SDIO_IRQn);
     
@@ -1186,7 +1271,7 @@ static void initSDIOPeripheral()
     SDIO->CLKCR=0;
     SDIO->CMD=0;
     SDIO->DCTRL=0;
-    SDIO->ICR=0xc007ff;
+    SDIO->ICR=ICR_FLAGS_CLR;
     SDIO->POWER=SDIO_POWER_PWRCTRL_1 | SDIO_POWER_PWRCTRL_0; //Power on state
     //This delay is particularly important: when setting the POWER register a
     //glitch on the CMD pin happens. This glitch has a fast fall time and a slow

miosix/arch/common/drivers/serial.h

@@ -3,7 +3,7 @@
 
 #ifdef _ARCH_ARM7_LPC2000
 #include "serial_lpc2000.h"
-#elif defined(_ARCH_CORTEXM0_STM32)   || defined(_ARCH_CORTEXM3_STM32)   \
+#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM3_STM32F1) \
    || defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32F2) \
    || defined(_ARCH_CORTEXM3_STM32L1) || defined(_ARCH_CORTEXM7_STM32F7) \
    || defined(_ARCH_CORTEXM7_STM32H7) || defined(_ARCH_CORTEXM4_STM32F3) \